Akash Banerjee AB
Akash Banerjee

Akash Banerjee

Compiler Engineer at AMD

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About Me

I'm a compiler engineer at AMD, UK. Currently part of the HPC compiler team for the Frontier supercomputing project, where I work on the new llvm‑flang driver for Fortran and device code offloading support for the OpenMP dialect in MLIR.

My interests lie in compilers, program analysis, formal verification and SAT solvers. I attained my master's in Computer Science & Engineering at IIT Hyderabad under Prof. Saurabh Joshi in the field of software verification and worked with Prof. Ramakrishna Upadrasta on improving compiler optimizations.

When I’m not coding you can find me losing games in DOTA 2, staring at my fish tanks or giving pats to Simba (OTRB). I’m also learning to use a camera 🙂

Skills

Programming

  • Proficient in C and C++
  • Experience with Java, Rust, Python, JavaScript and C#

Frameworks & Tools

  • Deep knowledge of MLIR & LLVM compiler infrastructure
  • Experienced with the CProver verification framework
  • Git, GDB, LLDB, Eclipse, LaTeX

Systems

  • Linux system administration
  • CI/CD build bots deployment & maintenance
  • Regression testing

Design Tools

  • Blender, ZBrush
  • Unity, Photoshop

Projects

Clang Migration

Feb 2023

Contributed to migrating the OpenMP codegen in Clang to the MLIR‑based OpenMPIRBuilder, enabling the OpenMP MLIR dialect and Clang to share code and improve quality while reducing duplication.

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OpenMP

Sep 2022

Added device offloading support features to the OpenMP dialect in MLIR. Our team was the first to achieve end‑to‑end kernel execution on device for the llvm‑flang driver. Received an AMD Spotlight award for this work.

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LLVM‑Flang

Sep 2022

Developing and adding language support — particularly for OpenMP — to the llvm‑flang driver for Fortran. llvm‑flang is the new MLIR‑based frontend for Fortran in LLVM.

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Proteus: Polymorphic Compilation

Jun 2021

Developed a compiler tool using polymorphic compilation and execution techniques to mitigate a class of side‑channel attacks with minimal performance overhead. Part of my master's thesis project.

BPI Enhancements

Apr 2020

Proposed and implemented improvements to the Branch Probability Information pass in LLVM to allow better static profiling. The enhancements led to speed‑ups of up to 1.07× and were accepted as a poster at EuroLLVM 2020.

Source Poster

Loop Acceleration

Oct 2019

Added a loop acceleration module to the Pinaka verifier for quick detection of counterexamples in loops simulating polynomial functions. Pinaka won the third‑fastest verifier position in SV‑COMP’20 Floats sub‑category.

Source

LLVM2GOTO

Sep 2019

Created a tool to translate LLVM IR to CBMC‑GOTO. This allows verification of programs that have LLVM front‑ends by translating their IR into GOTO IR and verifying them with CBMC.

Source

COOL Compiler

Aug 2019

Designed and implemented a compiler for the COOL language to generate LLVM IR as part of the Advanced Compiler Design course project.

SAT Solvers

Mar 2019

Implemented DPLL, CDCL, and MaxSAT solvers with various heuristics and techniques such as MOMS, lazy data structures, and watch literals as part of the Constraint Programming course project.

Source

Hybrid Mutual Exclusion

Nov 2018

Implemented a hybrid mutual exclusion algorithm for distributed systems by combining Raymond’s and Maekawa’s algorithms, multiplexing between them based on load, latency, and throughput.

Source

Thin Slicing in GOTO

Nov 2018

Implemented thin‑slicing in CBMC‑GOTO to aid debugging of large programs by presenting only relevant sections of code, improving focus and efficiency.

Bitcoin Wallet

Oct 2018

Developed a Bitcoin wallet application capable of creating and managing BTC addresses with support for single and multisig authorization. Completed for the Blockchain Theory & Practice course.

Source

Get in touch

Address

Regus – Midsummer Court
Milton Keynes MK9 2UB
England, United Kingdom